Semicon Europa adds design and smart-transportation seminars
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, aims to bring a design-oriented thread to the upcoming Semicon Europa show. Semicon Europa will begin Tuesday,...
View ArticleAccellera sets up to group to look at interoperability for safety analysis
Accellera has given the green light to a team to look at tool interoperability for building functionally safe systems. The organization has set up a proposed working group (PWG) to focus on a standard...
View ArticleMentor takes DFT planning to a higher level for hierarchical flows
Mentor, a Siemens business, has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies as multicore SoCs become more prevalent and complex. Geir...
View ArticleMRAM pushes speed and endurance at IEDM
Although it is a strong contender to replace flash as a non-volatile memory for SoCs, a problem for magnetic memory (MRAM) lies in its tradeoffs: you can have a memory cell that holds data long periods...
View ArticleClik here to view.
Deploying pre- and post-silicon verification and test for 5G designs
The 5G roll-out is posing major test and verification challenges for electronic system design. A new technical article reviews the differences between the new mobile standard and 4G and suggests...
View ArticleClik here to view.
Ultrawide neural engine fills a hole
One of the advantages of adding accelerators to multicore processors is that sometimes pad limits mean the area needed comes almost for free. When adding a neural-network unit to its latest x86-based...
View ArticleMentor to use UltraSoC acquisition to drive in-life learning
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC, aiming to fold the operation into Mentor’s Tessent test-software product portfolio. “Siemens’ acquisition of...
View ArticleClik here to view.
Chiplet design raises big questions
An online conference organized by the trade group MEPTEC last week (July 13-14, 2021) provided insights into how SoC design may evolve into system-in-package based on the use of chiplets. It is a...
View ArticleDAC 2021 preview: Breker Verification Systems
Breker Verification Systems, specialist in test content synthesis solutions for SoC, UVM and post-silicon verification environments, will showcase its latest innovations at this week’s Design...
View ArticleAMD moves gradually into 3D integration
At the recent Design Automation Conference, back in San Francisco with a hybrid format, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design...
View Article
